1. Field of the Invention
The present invention relates to an SRAM (Static Random Access Memory) cell and an integrated memory circuit using the same and, more particularly, to a circuit arrangement and pattern layout of an SRAM cell which is used for, e.g., an SRAM integrated circuit, SRAM-embedded integrated logic circuit, or the like.
2. Description of the Related Art
SRAM cells include a type comprising four MOSFETs (insulated gate type field effect transistors) and two load resistive elements and a type comprising six MOSFETs (6-transistor SRAM cell). Further, a type comprising five MOSFETs (5-transistor SRAM cell) is disclosed in U.S. Pat. No. 5,831,896.
FIG. 6 shows a butterfly curve representing the stability of a conventional 6-transistor SRAM cell. As is well known, first to fourth transistors in the 6-transistor SRAM cell constitute first and second inverters connected to form a flip-flop circuit which has first and second storage nodes. The first storage node which is an output node of the first inverter is connected to one of a pair of bit lines via a fifth transistor (transfer gate transistor) of the cell and the second storage node which is an output node of the second inverter is connected to the other of the pair of bit lines via a sixth transistor (transfer gate transistor) of the cell. Gates of the fifth and sixth transistors are connected to a word line.
FIG. 6 shows an input/output characteristic curve (transfer curve) C1 of the first inverter provided in one SRAM cell. The SRAM cell has first and second storage nodes. The characteristic curve C1 of the first inverter represents a relationship between a second storage node potential VNB as an input voltage along an abscissa x and a first storage node potential VNA as an output voltage along an ordinate y.
An input/output characteristic curve C2 of the second inverter in the SRAM cell represents a relationship between the first storage node potential VNA as an input voltage along the ordinate and the second storage node potential VNB as an output voltage along the abscissa. The word line and the pair of bit lines, which are connected to the SRAM cell, are biased to a power supply voltage VDD.
In FIG. 6, an intersection A between the two input/output characteristic curves C1 and C2 represents a state wherein the first storage node potential VNA is at a low level “L”, the second storage node potential VNB is at a high level “H”, and the SRAM cell holds “0” data.
Conversely, an intersection B1 between the two input/output characteristic curves C1 and C2 represents a state wherein the first storage node potential VNA is at a high level “H”, the second storage node potential VNB is at a low level “L”, and the SRAM cell holds “1” data.
The length of one side of the maximum square denoted by a broken line in FIG. 6 that is inscribed to two regions surrounded by the two input/output characteristic curves C1 and C2 is defined as a static noise margin SNM. Generally, the larger the static noise margin SNM is, the higher the cell data stability is. In other words, data destruction due to power supply voltage noise hardly occurs in a chip provided with the SRAM.
When devices or cells become small, the design rule decreases to, e.g., about 0.09 μm, the power supply voltage VDD lowers to, e.g., about 1.2V, and the static noise margin SNM becomes small. It is important to ensure a large static noise margin SNM in designing an SRAM cell.
Two methods are mainly available to design an SRAM cell having a large static noise margin SNM.
As the first method, the x-coordinate of a point C at which the first input/output characteristic curve C1 starts dropping from a high level “H” and the y-coordinate of a point D1 at which the second input/output characteristic curve C2 starts dropping from a high level “H” are set to large values, as shown in FIG. 6. To do this, a threshold value Vthna of each of two driver transistors arranged in the first and second inverters is increased. However, the current drivability of the driver transistors deteriorate accordingly to decrease the cell current, resulting in a decrease in data read speed of the cell.
As the second method, a potential VA at the y-coordinate of the intersection A between the two input/output characteristic curves C1 and C1 and a potential VB1 at the x-coordinate of the intersection B1 are set to small values, as shown in FIG. 6. The potential VA corresponds to the first storage node potential VNA when the input of the first inverter is the power supply voltage VDD.
To decrease the potential VA, the current drivability of the transfer gate transistor may be decreased, or the current drivability of the driver transistor may be increased, as is known.
However, when the current drivability of the transfer gate transistor is decreased, the cell current decreases, resulting in a decrease in the data read speed. When the current drivability of the driver transistor is increased, the cell area increases, as is known.
As described above, in the conventional SRAM cell and an integrated memory circuit using the SRAM cell, if the static noise margin SNM indicated in the butterfly curve is increased to improve the stability of cell data the read speed decreases due to a decrease in cell current, or the cell area increases.